MXR 129 Pitch Transposer Circuit Description R Grieb 5/26/2016 First I should mention that I never worked at MXR and had nothing to do with the design of the MXR 129. I am trying to help people who are interested in repairing their units to understand how it works. This is a somewhat complex design, so there may be mistakes in this document. Since I have no way to draw lines over signal names in this document, I will indicate active-low signals with a lower case b at the end instead. LOWER BOARD CIRCUITRY: The lower board selects one of the four preset controls, amplifies and filters the input signal, filters the output signal, and generates the two sample rate clocks (write and read) which determine the amount of pitch shift. The two sample clocks are fed to the upper board, and also to the optional display. These clocks are all that is needed by the display unit to determine the pitch shift amount. The power supply rectifier, filter, and regulator components are also mounted on the lower pcb. Input signals are amplified by U1 and U3. The gain of U3 is controlled by the Level switch. The output of U3 passes through two 12 dB/octave low-pass filters (U4) before feeding to the upper board. The output signal comes from the upper board, and is fed through two 12 dB/octave low-pass filter stages (U5). Then it feeds into the S2 level switch and through U3. The output circuits use an analog switch IC to select either the output signal from the upper board, or the input signal in bypass mode, or a mix of the two. The Regen control adds a variable amount of the pitch-shifted output to the input signal. The preset selector uses an RC oscillator (U9-13,12) to drive the knob surfaces. The oscillator also drives the clock input to a 5-bit register (U10). When a knob is not touched, the signal on it is not delayed, and is captured in the high state by the register U10. If a knob is touched, the external capacitance delays the signal a little, and it is captured in the low state by U10. So if a knob is touched, one output of U10 will be low. This means that one output of U9 will be high. The active output is encoded by U11 into a 3-bit binary code. The low two bits of the code feed U12 A and B inputs to select one of the Y outputs to be +15V. This will turn on the correct LED. Also, when the knob is no longer touched, the active D0-D3 input to U11 will become the highest priority input and will hold the values at U12 A and B. (Pretty clever) When one of the knobs is touched, one of the D4-D7 inputs to U11 will be high. This will set the U11-Q2 output high, which will reset the RS latch formed by U8, turning off bypass mode if it was on. NOTE: On my unit, all of the presets activated their bits in U10 when touched, but touching the bypass button had no effect. I was not able to make it switch no matter how I touched it. I was able to make it work nicely by changing R34 from 47K to 68K. When I made it 100K, the button was always activated, even when not touched. 56K still didn't make it work. It started to switch reliably at 62K, so I settled on 68K to give it a little margin. One of the four preset control voltages is selected by U12 at pin 13. The selection is made by U12 pins 9 and 10, which are part of the preset LED circuit, and are fed by U11 based on which knob is being touched. The write and read sample clocks are generated using 555 timers IC's configured as astable oscillators. Their frequency is changed by the potentiometer setting, via U13 and U14. To shift pitch up, we would read faster than we write, so the read clock would have a higher frequency. To shift pitch down, we read slower than we write. U13-7 sits at 10VDC. So the junction of R105 and R114 sits at 2/3 of that, or 6.67VDC That voltage is also at pins 3 and 5 of U14. When the selected potentiometer is at mid position, it will have 5VDC on its wiper, and at U12-13. U13-1 would also be at this level. The current through R112 would be (5-6.67)/150K, or -11.1 uA into pin 2 of U14 from U13-1. By the same token, the current from U13-7 would be (10-6.67)/300K, or +11.1 uA. So when the pot is centered, the net current into U14-2 from the two inputs is 0. In that case we would expect the output to be at 6.67V as well, and U14-7 would also be at 6.67V So in that case, we would expect both 555's to be oscillating at the same frequency (~40 KHz). If the pot is turned towards ground (CCW or transpose down), then U13-1 will decrease, causing U14-1 to increase. This will forward-bias diode CR6, selecting R107,8,9 as the feedback components for U14-1,2,3. If the pot is turned towards 10V (CW or transpose up), U14-1 will decrease, forward-biasing CR7 instead, and selecting R110,111,113 as the feedback for U14-1,2,3. So the feedback around U14 varies depending on which way the pot is turned away from center. In addition, A2 would see its pin 5 control voltage increase only when the pot is turned towards ground, and A3 would see an increase only when the pot is turned towards 10V. A2 is generating the read clock. When the preset pot is centered, or turned to pitch increase, the read clock is at about 40 KHz. When the pot is turned to pitch decrease, the read clock slows down, reaching about 20 KHz at full CCW rotation. When the pot is centered, or turned to pitch decrease, the write clock (A3-3) is at about 40 KHz. When the pot is turned to pitch increase, the write clock slows down, reaching about 20 KHz at full CW rotation. When the pot is centered, both clocks should be about 40 KHz, and should be equal. U14-1 drives the base of the Q10 and Q11 pair, which sets the current into the gain control pin of a CA3080 OTA (U31) on the upper pcb. U31 is part of the output splicing control circuit. UPPER BOARD CIRCUITRY: The upper board samples the input waveform, converts it to an 8-bit digital value, and stores it in a circular memory buffer. It does this at a rate determined by the write clock from the lower pc board. It also reads 8-bit values from the same circular buffer, converts them back to analog voltages, and sends them to the lower board for output. It does this at a rate determined by the read clock from the lower pc board. Separate read and write addresses point into the same buffer, and are used for the corresponding operation. When the write clock goes high, it generates a short high pulse at U24-4, which turns on Q1, pulling down SWREQb momentarily. This clears the Qb output of RS-latch formed by U1-3,11. U7 pin 8 goes high, enabling counter U2. U2 is clocked by the main clock and steps through the write sequence. The high pulse at U24-4 is also fed to A1-13 analog switch, which samples the input signal on capacitor C18. C18's voltage is buffered by U28-5,6,7 and fed into comparator U29. Similar circuitry is used to initiate a read sequence when read clock goes high. Writing and reading require a number of clock cycles per operation, so a clock that runs at a higher frequency than the sample clocks is needed. This "main clock" is generated by U6, and has a frequency of about 1.35 MHz. A specific sequence of events must take place each time a sample is written to or read from memory. Somehow we need to generate the signals to control the different operations of this sequence. In this design, a counter (U2) and a small memory chip (U3) are used to step through the read or write sequence each time. The PROM memory chip holds 32 8-bit values, which were programmed at manufacture and never change. The outputs of the memory are registered by U4, to form the control signals needed to read or write a sample. The most significant address input (ADE) to the memory chip is connected to a R/Wb signal, so the counter walks through the upper 16 addresses for a read sequence and the lower 16 addresses for a write sequence. Normally a counter might count 0,1,2,3,4,5,6,7,8,9, up to 15. But here the designers also wanted to use several of the counter outputs directly as control signals, so they modified the count sequence by loading it with 8 when it reaches the count of 5, so the sequence looks like 0,1,2,3,4,5,8,9,A,B. Counter outputs QC and QD are registered by U4 along with the PROM outputs, and are used as RA0 and WA0. To end the write sequence, pin 7 of the PROM chip pulses low. This increments the write address counter, and also resets the write RS latch (U1) via U1-2. This latch enables the counter during write operations, and is set by the SWREQb signal, which is derived from the write clock. The same counter and small ROM chip are used for reading or writing, so we can only do one of those operations at a time. The circular memory buffer is implemented using four 4Kx1 dynamic RAM chips. All four chips share the same address, so together they can store 4096 4-bit values. But our samples are 8 bits wide, so we need to divide them into two 4-bit values and store them in separate addresses. So each sample write operation must write two values to two different addresses. WA0 is the least significant bit of the write address bus, and is controlled directly by the PROM. RA0 works the same way. A 4K buffer requires 12 address lines. The lowest address lines are WA0 and RA0, which are controlled by the PROM. The upper 11 bits, which select a particular sample, are implemented by the counters U38 and U39 (write address) and U9 and U39 (read address). These counters are incremented at the end of a write or a read sample operation by signals coming from the PROM. The 4K DRAM chips need 12 address lines to select the data, but only six pins are used. These chips use a multiplexed addressing scheme that is common with DRAMs. The memory is implemented as a matrix with rows and columns of bits. Six address lines select a particular row, and the other six select a particular column in that row. So we have used all 12 address lines, but we don't use them all at the same time. The row is selected first, then the column, then the write or read happens. So these chips have RASb (row address strobe) and CASb (column address strobe) inputs. First the six-bit row address is fed to them and RASb goes low, then the six-bit column address is fed to them and CASb goes low. The advantage of this is that the chip needs fewer pins, so it can be less expensive and smaller. But the design is more complicated. The PROM generates a RAS signal, which is inverted by U8-12,13,11 to make RASb. That signal is delayed a little to make RCSEL, so that the addresses change a little bit after the RASb signal has gone low to the DRAMs. Then another delay is added by R4,C6 before the signal becomes CASb to the DRAMs. So the same output from the PROM is used to make all three signals, the second and the third just being delayed versions of the first one. Chips U10,U12,U11 are multiplexers which select the correct address lines to feed to the DRAM chips. We need to select between the read address and the write address, depending on the operation, and also between the row address lines and the column address lines, because we are using DRAMs. The R/Wb signal at pin U10-2 selects between read or write addresses, and the RCSEL at U11-14 selects between the row and column part of each address. We need to convert our analog input voltage into a digital value so that we can write it to memory. C18 holds the sample that we want to convert. One way to perform an analog-to-digital conversion is with a DAC and a comparator. A "successive approximation" chip can control the DAC and step through different digital values to find the one that matches the voltage to be converted. After each step is taken, the comparator tells this chip if the DAC voltage is too high or too low, and the chip choses the next step based on this. Normally this process takes about 8-10 clock cycles for an 8-bit conversion. U21 is the successsive- approximation chip in this design. It is clocked at the 1.3 MHz rate, so 10 cycles would take about 8 uSec. Conversion is initiated by the STARTb signal which is generated by the PROM. It will only be active for sample write operations, since that is when we need to convert an analog value into digital form. If we are sampling at 40 KHz, then we have 25 uSec to sample the signal, convert it, and write it to memory. But we also may need to read a sample, and we can't do both at the same time, so we stay pretty busy. Anyway, when we are converting an analog voltage on C18 to a digital value, U19 is enabled to feed U21 to the DAC (A4). When the conversion is finished, the digital final value will be sitting on the outputs of U21, and can be fed via U20 (4 bits at a time) to the memory data in bus. When we read samples out of memory, we need to convert them back to voltages. This is done using the same DAC, but in this case, two 4-bit values which have been read from memory are stored in U17 and U18. Both edges of the RA0 line are used to clock the DRAM read data into U17 and U18. U19 outputs are disabled, and U17,18 outputs are enabled, so the DAC gets the sample value read from memory and converts it into a voltage. That voltage is stored on either C26 or C27 by enabling either A2-13 or A2-12. The DAC used here (Am6072 or DAC88) is an 8-bit "companding" one, which has a non-linear mapping of digital values to analog ones. This improves the dynamic range and signal/noise ratio, for audio use, versus a conventional 8-bit DAC. Since the same DAC is used for A->D and D->A, the non-linearity is applied both times and will cancel. THE TRICKY BIT: We have separate read and write addresses (pointers) into our 2K-sample circular sample memory buffer. Each time we read out a sample, we increment the read pointer, and each time we write we increment the write pointer. Since it's a "circular buffer", when a pointer gets to the end of the buffer, we simply wrap it back to the first address. Pointers are always incremented (not decremented). If we are writing to a circular buffer at a higher rate than we are reading, pretty soon the write pointer will catch up to the read pointer. Likewise if we are reading at a higher rate than we are writing, the read pointer will overtake the write pointer. When this happens, the two pointers are equal. IC U40 checks for this condition by comparing the upper bits of the two addresses. The output at pin 19 will go low when the upper eight lines of the read and write addresses match. If we didn't do anything special when the two pointers are equal, we would get a discontinuity in the output waveform, as the read sample jumps in time to a different part of the stored waveform. To address what would otherwise be a "glitch" in the waveform, we read two samples at a time, from two different places in the buffer which are exactly 1024 samples apart. During reads, the signal WA0 is not needed for write addressing, so it can be used for another purpose. WA0, which comes from the PROM, is low during the first half of a read sequence, and high during the second half. This signal is used to invert RA11, the most significant bit of the read address, to the SDRAM chips via U8-4,5,6. The signals SOUT1b and SOUT2b indicate which of the two samples is being read at a given time, and are used to latch the voltage from each sample into C26 or C27. So we are not reading one stream of samples from the buffer, but two streams, separated by 1024 samples, which is exactly half of the buffer. Each time the read clock tells us to read a sample, we actually read two, convert them to voltages, and latch those voltages into C26 and C27. These voltages are sampled again by A3-13,6 and appear at the outputs of U14 as two waveforms (one a delayed version of the other). Both of these waveforms will have glitches in them when their pointers collide, but since there is only one write pointer, and the two read pointers are 1024 samples apart, they will collide at different times, and the glitches will occur at different times. So when one stream is glitching due to the pointers colliding, we have another stream that is not glitching and we can use that one instead. But the two streams are delayed from each other by 1024 samples, so switching between them can also cause a glitch in the output. The goal is to feed out a single stream that is derived from the two streams, but which is not using the stream that is glitching right when the glitch happens. A10 allows us to select varying amounts of the signals from the two streams for output, so we can switch away from the stream that has the glitch and use the other one. After U14, each stream is fed through an op amp with a gain of -1 (U15). The two stream voltages before and after the inverters are fed to two analog switches, so that the polarity of each signal can be selected before feeding into each half of A10. The address comparator U40 indicates when the read address and the write address are equal. There are two read addresses, one for each of the two streams. They are exactly 1024 samples apart, which means that all of the bits are the same except for RA11. The signal CSEL controls whether RA11 is inverted or not, as it is fed into the address comparator. So this signal selects if we are looking for a match on read stream 1 or stream 2. When a match occurs, Q10 turns on as its base is pulled low by R103. This applies a high level to pin 10 of U27, resetting this flip flop. This causes the Qb output to go high, clocking U27-3. This flip flop is configured to toggle whenever it is clocked. When it changes state, the base of Q9 also changes, and CSEL changes. This inverts the polarity of RA11 from whatever it was when the match occured, effectively switching to looking for a match on the other stream. So every time there is a match, we initiate some activity, and also switch to waiting for a match on the other stream. As we said before, the glitches that we need to smooth out with "splicing" occur when the read address matches the write address. As mentioned above, when an address match occurs, we get a change of state on U27-1,2 outputs. One of them will go high and the other will go low. The one that is going high clocks its half of U37. So one half of U37 is clocked when stream 1 address match occurs and the other half for stream 2. The outputs of these two flip flops are used to select the polarity of the two streams, by controlling A9. So for each stream address match, the polarity of one of the streams is selected by clocking one of the flip flops. And we are constantly alternating between the address matching on each stream. The D inputs of the two flip flops are fed from the Q output of the other flip flop, so the polarity information is constantly passed back and forth from one flip flop to the other when clocking occurs. Each half of U25 monitors one of the two read sample streams. Capacitors C54, C55 will tend to charge to the average DC level of each waveform. If the non-inverting input is higher than the capacitor voltage, the output will be high, which will tend to increase the voltage on the capacitor. With the capacitor tracking the average level of the signal, the output of the op amp then becomes an indication of whether the signal is in a positive portion of the waveform or a negative one. Since we have this same signal for each of the two streams, we can feed them into an XOR gate (U16) to compare them. If both waveforms are above their average level, the output of the XOR will be 0. If both are below, the output will also be 0. But if one is above and one is below, the output of the XOR will be 1 (high). Now if we integrate the output of the XOR (U22-1,2,3) we get a voltage that indicates whether the two waveforms tend to be positive and negative at the same time, or if they are more tending to be opposite polarities of each other. The output of the integrator is fed into U25-11,10,13, set up as a comparator. The output of the comparator is used to determine whether we should flip the polarity when we switch from one stream to the other to avoid the glitch/discontinuity caused by the address match/buffer over/underrun issue. U25-13 controls whether the polarity changes as it is clocked from one flip flop into the other. The polarity that we should select depends on the frequency of the input waveform. The delay between the two streams is determined by the read sample rate, and is fixed for a particular pitch shift setting. But the frequency of the input signal is variable, and it's most likely a complex waveform, not a simple sine wave. But still we can determine whether inverting the streams with respect to each other will make them closer to the same level or further apart. We are trying to smooth out the transition from one waveform to the other that we need to make to avoid the glitches. The rate at which we need to fade from one stream to the other depends on the pitch transposition amount. The more we are transposing, the greater the difference between the read and write sample rates, and so the more often the buffer over/underrun occurs. At maximum transposition, the transition between the two streams happens roughly every 50 mS. Each half of A10 is a variable gain amplifier. The gains are controlled by the currents into pins 2 and 15 of A10. The audio output is taken from a point halfway between the outputs of the two amplifiers. So we can think of A10 as a sort of mixer with two inputs. The currents that control the two amplifiers in A10 come from Q6,Q7,U35, and U34. This circuit is arranged so that when one amplifier's gain is increased, the other one is decreased, and vice versa. So we have two audio streams, each of which can either be inverted or fed directly into A10, and the audio output is taken from the midway point between the two A10 amplifier outputs. A10 is used to fade between the two streams to create the output signal. As mentioned above, the outputs of U27 toggle each time we get an address match condition for one of the streams. At this time we fade toward the stream that is not glitching and away from the one that is matching to avoid its glitch/discontinuity. This toggling is due to feeding U27-1 through OTA U31 and into U34, which is the control for fading between the two amplifiers in A10. As U27-1 toggles, it fades toward one stream or the other, in sync with the waveform polarity selection that was discussed above. The control currents from Q6 and Q7 collectors tend to move in opposite directions when we switch streams, as discussed. The input signal from the lower board is fed into U32-5 by C46. U32 and U33-6,7,8 are configured as a precision full-wave rectifier circuit with filtering provided by C51. So the output at U33-7 is a dc level related to the level of the input signal to the pitch transposer. But the gain of U32-5,6,7 is 100, so this amplifier (which is powered from +/-7.5V) saturates when the input signal level exceeds about 160mV pk-pk. This signal and it's inverse (U33-1) are fed into the circuit that controls the gain of the A10 amplifiers in such a way that when the input signal is very low, the control current swing is very small. Perhaps this is sort of a noise gate, as the gains of both A10 sections are reduced when there is no input signal, and full swing of the gain controls is achieved with just 160 mV pk-pk input signal. U22-5,6,7 amplifies and buffers the signal from A10 before it is fed to the lower board.